Technology Barriers on Large Diameter Sapphire Substrates

The second barrier to the adoption of large diameter sapphire substrates is a group of technological hurdles. It begins with challenges in sapphire crystal growth–the first step in creating sapphire substrates.Today’s sapphire for HB-LEDs is typically grown on the a-axis, even though HB-LEDs require c-axis wafers. To get c-axis wafers from a-axis sapphire boules, a core must be taken sideways – wasting a large part of the sapphire.

Today’s a-axis sapphire growth technologies also result in defects that cannot be avoided when coring for large diameter applications. The volume of a 6- or 8-in core is so large that the defects become unavoidable and the cores must be shortened or scrapped. The total losses from sideways coring and defects waste over 80% of the material. For 8-in applications, the waste is over 90% and the production costs double.

Another barrier caused by a-axis growth is that the resulting wafers have a variation in stress and strain across their surface. Because the wafer is from a sideways core of the boule, and the boule is grown along the a-axis, the wafer itself has a long growth time signature across its surface. This becomes significant during epitaxial growth when the wafer is heated.

As you can see in the Fig. 6, the wafer will bow in an uneven pattern or a warp. This warping is very difficult to counteract by the MOCVD engineer and has caused several attempted workarounds, including a move to thicker wafers and the use of stress-relieving layers. These techniques add to the production cost and complexity. Without counteracting the warp, the result during epitaxy is lower LED chip yield.
The last technology barrier is in the slicing and polishing of the wafer and application of PSS techniques. Slicing and polishing are difficult processes and must be done well to generate good yield during epitaxy. Because the large wafers are 9-16× larger, the difficulty increases significantly.

PSS application faces a similar challenge, with the additional obstacle that the pattern can only be seamlessly applied to a limited size area smaller than 6 in. In order to get PSS on a 6-in wafer, a stepper (a semiconductor manufacturing tool) must apply multiple patterns, which is common in the silicon industry. However, for HB-LEDs the edges of the multiple pattern applications must be closely matched or LED yield will drop. This accuracy requirement is proving to be very challenging.

These barriers of market conditions and technology challenges have created multiple limitations for the mass adoption of large-diameter substrates. In the future, the market demand will require the throughput and yield only available using larger substrates, and as a result the technology challenges will be overcome. As proof of the possibility of overcoming the challenges, several tier-1 manufacturers have already made the switch and are positioned with an advantage over the majority of the industry.


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