On WSe2, MoS2 And Graphene to Produce Ultra-Thin Dielectrics

On tungsten diselenide (WSe2), molybdenum disulfide (MoS2), and graphene to produce ultra-thin dielectrics for developing a new design strategy for manufacturing 2-D electronic devices. Two-dimensional semiconductors can have very useful applications, especially as channel materials for low-power transistors. These materials exhibit extremely high mobility at extremely high thicknesses, which makes them highly promising alternatives to silicon in the manufacture of electronics.

Despite their advantages, the application of these materials to transistors has so far proved challenging. In fact, two-dimensional semiconductors are of a bond-free nature. Therefore, it is well known that it is very difficult to place high-conductivity high-gate dielectric gates (i.e., substances with dielectric properties or insulators) on the materials by atomic layer deposition (ALD), which often results in discontinuous membranes.

new design strategy for manufacturing 2D electronic devices using ultra-thin dielectrics image

Researchers at Nanjing University in China recently proposed a new strategy to overcome this limitation, which eventually allowing dielectric gate deposition on 2-D semiconductors. In a paper published in Natural Electronics, they reported on the successful ALD of high-density gate dielectrics in 2-D semiconductors using a molecular crystal as a seeding layer.

Xinran Wang, one of the researchers who conducted the study, told Tech Xplore: "Our research is trying to solve the issue of high-quality 2-D transistor integrator gate integration." "In state-of-the-art Si transistors, the effective oxide (EOT) thickness has been reduced to sub-1 nm. Currently, there is a large gap between the 2-D and Si materials in EOT terms, the interface state density. and gate leakage. If one wants to seriously promote 2-D transistor technology, this gap must be overcome."

The method introduced by Wang and his colleagues allows the production of dielectrics with an equivalent thickness of 1 nm oxide in graphene, MoS2, and WSe2. Dielectrics produced by researchers' methods show reduced roughness, interface state density, and leakage compared to conventional methods. Interestingly, they also provide improved distribution area.

Wang added: "In addition to the 2-D transistors, another direction my research team is exploring is biological electronics." "In recent years we have developed tools for precisely controlling the fusion of molecules on a 2-D material surface. For many molecules, including PTCDA, we have proven that we can control growth so well that only one monolayer (~ 0.3 nm) is evenly filed, with a very clean interface."

The interface layer created by Wang and his research team in previous work is one of the thinnest interface layers currently available. In their current research, they used this layer for the manufacture of 60 GHz graphene radio frequency transistors, as well as for semiconductor MoS2 and WSe2 transistors with a supply voltage of 0.8 V and a low inclination of 60 mV dec-1. Finally, they also used their technique to create a MoS2 transistor with a 20 nm channel length with an on or off ratio of more than 107.

"I think the most important result was that we were able to achieve 1 nm EOT in 2-D materials," Wang said. "It is widely believed that the 2-D channel can reduce transistor power consumption compared to bulk semiconductors. However, to achieve this, we need to use the same operating voltage and transistors can shut off close to 60 mV. Both quantities depend largely on the quality and thickness of the dielectric gate."

Wang and his research team develop ultra-thin dielectrics on WSe2, MoS2, and graphene for manufacturing 2-D electronic devices. They successfully develop a 2-D transistor with a 1-nm EOT, and successfully deposited a dielectric on three different materials. Strikingly, the EOT and gate leakage they achieved are comparable to those observed in the latest silicon CMOS, which is an important step forward in this research area.

 

 

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